1. Field of the Invention
The present invention relates to a chopper type differential amplifier, and more particularly to a chopper type differential amplifier in which input signals are supplied via MOS gate capacitors precharged to specified potentials.
2. Description of the Prior Art
A differential amplifier to which input signals are supplied via capacitors precharged to predetermined potentials is generally called a chopper type differential amplifier. Since the amplitude of the input signals can be taken large in the chopper type differential amplifier, it is used widely in A/D converter or the like.
In order to simplify the manufacturing process, the so-called MOS gate capacitor in which the transistor structure is employed as a capacitor to receive the input signal, has been used in the past. This kind of chopper type differential amplifier will be described by making reference to FIG. 1. The lower electrode side of a MOS gate capacitor CG1 is supplied with an input signal VI(+), and the gate electrode side of CG1 is connected to one of the input ends (noninverting input side) 2 of a differential amplifier 1. Similarly, the lower electrode side of a MOS gate capacitor CG2 is supplied with an input signal VI(-), and the gate electrode side of CG2 is connected to the other input end (inverting input side) 3 of the differential amplifier 1. The input ends 2 and 3 of the differential amplifier 1 are connected to a precharging circuit 40 which precharges both input ends 2 and 3 to a potential of Vdd/2 during the precharging period.
The precharging circuit 40 comprises N-channel MOS-FETs QN31 and QN32 whose gate electrodes receive a sampling signal S31, drain electrodes are connected to a precharging voltage terminal 4 and source electrodes are connected to the input terminal 2 and the input terminal 3, respectively, of the differential amplifier 1, and P-channel MOS-FETs QP31 and QP32 whose gate electrodes receive a sampling signal S32, drain electrodes are connected to the precharging voltage terminal 4 and source electrodes are connected to the input end 2 and the input end 3, respectively, of the differential amplifier 1. The precharging voltage terminal 4 is provided with a voltage of Vdd/2 in contrast to the power supply voltage Vdd supplied to the differential amplifier 1 via a power supply voltage terminal 6.
The reason for using Vdd/2 as the precharging voltage is as described below. If the precharging voltage is chosen to be Vdd, then the voltage of the input end 2 or 3 of the differential amplifier 1 will be raised to beyond Vdd in response to the changes in the input signal. What will become of problem here is that the sources of the P-channel transistors QP31 and QP32 that constitute the precharging circuit 40 are connected to the input ends 2 and 3, respectively. In the P-channel transistor, P-type source and drain regions are formed on an N-type well region. Since the N-type well region is generally biased Vdd, there arises a problem that a forward bias condition of a P-N junction is generated in the P-type source regions to which the input ends 2 and 3 are connected, if the potentials of the regions become higher than Vdd.
Accordingly, if the maximum variations in the input signals are assumed to be .+-.Vdd/2, the precharging voltage must be set to be lower than Vdd/2 in order for the voltages of the input terminals 2 and 3 not to exceed Vdd.
An example of the MOS gate capacitors CG1 and CG2 shown in FIG. 1 is illustrated in FIG. 3. An N-type diffused layer 10 working as the lower electrode is formed in an N-type well 8 formed in a P-type silicon substrate 7, and a gate electrodes 11 is formed via an insulating film.
Next, referring to FIG. 2, operation of the chopper type differential amplifier shown in FIG. 1 will be described.
First, input signals VI(+) and VI(-) are applied to the lower electrodes of the MOS gate capacitors CG1 and CG2 respectively, and the sampling signal S31 goes to a high level. Consequently, the N-channel MOS-FETs QN31 and QN32 are turned on. At the same time, the sampling signal S32 goes to a low level, and the P-channel MOS-FETs QP31 and QP32 are also turned on. As a result, the input end 2 and the input end 3 (the gate electrodes of the MOS gate capacitors CG1 and CG2) of the differential amplifier 1 are precharged to the voltage of Vdd/2.
Subsequently, simultaneous with the shifting of the sampling signal S31 to the low level and the turning-off of the N-channel MOS-FETs QN31 and QN32, the sampling signal S32 goes to the high level and the P-channel MOS-FETs QP31 and QP32 are also turned off, and the charges stored in the MOS gate capacitors CG1 and CG2 are conserved. Then, the level of one of the input signals (it is VI(+) here) undergoes a change. For example, if the voltage of the input signal VI(+) is raised slightly as shown by the solid line in FIG. 2, the potential V(+) of the input end 2 of the differential amplifier 1 goes also to a potential which is slightly higher than Vdd/2 as shown by the solid line in the figure. Accordingly, the output signal VO from the output terminal of the differential amplifier 1 goes to a high level as shown by the solid line in the figure.
On the other hand, when the input signal VI(+) drops slightly as indicated by the broken line in the figure, the potential V(+) of the input end 2 of the differential amplifier 1 goes to a potential slightly lower than Vdd/2 as shown by the broken line, so that a low level output signal VO is output from the output terminal of the differential amplifier 1.
The conventional chopper type differential amplifier can detect a slight difference in the input signal as described in the above.
The conventional chopper type differential amplifier 10 has a problem in that the MOS gate capacitor has a depencence on the bias so that the device tends to undergo malfunction by generating an unbalance in the input impedance depending upon the potential of the input signal, and being affected by the noise. The reason for this will be described in the following.
In general, the capacitance CG of the MOS gate capacitor can be represented by either of the following two expressions depending upon the bias voltage applied (in the following discussion, the case of a MOS gate capacitor with a structure as shown in FIG. 3 will be adopted for the reason of simplicity).
1. Case of VGS&gt;0 V EQU C.sub.G =COX. (1) PA0 2. Case of VGS&lt;0 V ##EQU1## In Eq. (2), X.sub.SiO.sbsb.2 is the relative permittivity of the gate insulating film,
X.sub.Si is the relative permittivity of silicon, PA1 .epsilon..sub.0 is the permittivity of vacuum, PA1 q is the charge on the electron, PA1 N.sub.D is the impurity concentration of silicon crystal, PA1 t.sub.OX is the thickness of the gate insulating film, PA1 C.sub.OX is the capacitance of the gate insulating film, and PA1 V.sub.GS is the voltage difference between the gate electrode and the lower electrode.
Thus, it is assumed, for example, that the impurity concentration of the N well is N.sub.D =5.times.10.sup.18 cm.sup.-3 and t.sub.OX =15 nm in the MOS gate capacitor shown in FIG. 3, the MOS gate capacitance CG shows a bias dependence as shown by the solid line in FIG. 4. Here, if the potentials of the input signals are in an unbalanced relation in which, for example, VI(+)&gt;Vdd/2 and VI(-)&lt;Vdd/2, the MOS gate capacitance CG1 is biased negatively (VGS&lt;0 V) while the MOS gate capacitance CG2 is biased positively (V.sub.GS &gt;0 V). From this result, as is clear from the bias dependence shown by the solid line in FIG. 4, the capacitances of the two MOS gate capacitors CG1 and CG2 show an unbalance CG1&lt;CG2.
If an in-phase noise creeps into the two input ends 2 and 3 of the differential amplifier 1 in this state by, for example, the injection of the same electric charges, the input potentials to the input ends 2 and 3 of the differential amplifier 1 become potentials with different amplitude as shown by VV(+) and VV(-) in FIG. 2. Accordingly, an erroneous output signal as shown by WO is output from the output terminal of the differential amplifier 1.